Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37115 )
Change subject: sb/intel/bd82x6x: Support ME Soft Temporary Disable Mode ......................................................................
Patch Set 13:
(6 comments)
https://review.coreboot.org/c/coreboot/+/37115/5/src/mainboard/lenovo/x230/c... File src/mainboard/lenovo/x230/cmos.default:
https://review.coreboot.org/c/coreboot/+/37115/5/src/mainboard/lenovo/x230/c... PS5, Line 17: Disable
I think I'll turn it into enum me_state with values Normal and Disabled.
Done
https://review.coreboot.org/c/coreboot/+/37115/5/src/mainboard/lenovo/x230/c... File src/mainboard/lenovo/x230/cmos.layout:
https://review.coreboot.org/c/coreboot/+/37115/5/src/mainboard/lenovo/x230/c... PS5, Line 76: 0
This refers to CMOS enumeration #0, which is like #1 but "wired" backwards. […]
Not relevant anymore.
https://review.coreboot.org/c/coreboot/+/37115/5/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/me.h:
https://review.coreboot.org/c/coreboot/+/37115/5/src/southbridge/intel/bd82x... PS5, Line 190: #define MKHI_HMRFPO_ENABLE 0x01
Is it me, or are these hex values not aligned?
Done
https://review.coreboot.org/c/coreboot/+/37115/5/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/me_8.x.c:
https://review.coreboot.org/c/coreboot/+/37115/5/src/southbridge/intel/bd82x... PS5, Line 523: struct device *lpc = pcidev_on_root(0x1f, 0); : u32 etr3 = pci_read_config32(lpc, ETR3)
Moved to a separate file.
Not sure. Is this a problem?
https://review.coreboot.org/c/coreboot/+/37115/11/src/southbridge/intel/bd82... File src/southbridge/intel/bd82x6x/me_common.c:
https://review.coreboot.org/c/coreboot/+/37115/11/src/southbridge/intel/bd82... PS11, Line 21: int
boolean
Done
https://review.coreboot.org/c/coreboot/+/37115/11/src/southbridge/intel/bd82... PS11, Line 28: #endif
Yes.
Done I guess.