[coreboot-gerrit] Change in coreboot[master]: vendorcode/amd/agesa/f12/Proc/CPU: Fix set MTRR6 and MTRR7 to default

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[e-mail] has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36000 )

Change subject: vendorcode/amd/agesa/f12/Proc/CPU: Fix set MTRR6 and MTRR7 to default
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vendorcode/amd/agesa/f12/Proc/CPU: Fix set MTRR6 and MTRR7 to default

Incorrect comparison operator led to code never executing.

Change-Id: I78061491c16fbb51acfd8347e1eae011ff19a390
Signed-off-by: Joe Moore 
---
M src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/36000/1

diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c
index 57483a9..0bdc7cb 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c
@@ -149,7 +149,7 @@
       }

// restore variable MTRR6 and MTRR7 to default states
-   for (msrno = 0x20F; msrno <= 0x20C; msrno--)  // decrement so that the pair is disable before the base is cleared
+   for (msrno = 0x20F; msrno >= 0x20C; msrno--)  // decrement so that the pair is disable before the base is cleared
       __writemsr (msrno, 0);

// Enable fixed-range and variable-range MTRRs