[coreboot-gerrit] Change in coreboot[master]: soc/intel/broadwell/pch/sata.c: Don't enable Bus Master

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47026 )

Change subject: soc/intel/broadwell/pch/sata.c: Don't enable Bus Master
......................................................................

soc/intel/broadwell/pch/sata.c: Don't enable Bus Master

Bus Master is not required and reference code does not set it.

Change-Id: I2f70486f96cf3dcaba74283293b93b9747cd0300
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47026
Tested-by: build bot (Jenkins) 
Reviewed-by:  Felix Singer 
---
M src/soc/intel/broadwell/pch/sata.c
1 file changed, 2 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
   Felix Singer: Looks good to me, approved

diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/soc/intel/broadwell/pch/sata.c
index b496e53..82760ab 100644
--- a/src/soc/intel/broadwell/pch/sata.c
+++ b/src/soc/intel/broadwell/pch/sata.c
@@ -35,9 +35,8 @@

printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n");

-	/* Enable BARs */
-	pci_write_config16(dev, PCI_COMMAND,
-			   PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+	/* Enable memory space decoding for ABAR */
+	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO);

/* Set Interrupt Line */
    /* Interrupt Pin is set by D31IP.PIP */