Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38737 )
Change subject: soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38737/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38737/1//COMMIT_MSG@7 PS1, Line 7: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
soc/intel/tigerlake
Done
https://review.coreboot.org/c/coreboot/+/38737/1//COMMIT_MSG@11 PS1, Line 11: tigerlake
Tiger Lake
Done
https://review.coreboot.org/c/coreboot/+/38737/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/38737/3/src/soc/intel/tigerlake/chi... PS3, Line 235: USB4/TBT
This is a different config than ITbtPcieRootPortEn... […]
Done
https://review.coreboot.org/c/coreboot/+/38737/4/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38737/4/src/soc/intel/tigerlake/rom... PS4, Line 125: m_cfg->TcssItbtPcie0En = config->TcssItbtPcie0En; : m_cfg->TcssItbtPcie1En = config->TcssItbtPcie1En; : m_cfg->TcssItbtPcie2En = config->TcssItbtPcie2En; : m_cfg->TcssItbtPcie3En = config->TcssItbtPcie3En; :
we can but I was under the impression that this was a different setting and a loop really isn't usef […]
Done