Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86580?usp=email )
Change subject: cpu/x86/64bit: Allow to map more of the address space ......................................................................
cpu/x86/64bit: Allow to map more of the address space
On AMD platforms the SPI flash can be accessed using the ROM3 mapping in upper MMIO space. To reach the MMIO window the default page tables must be extended to cover the address by default.
Add support for a SoC specific default address space being used on x86_64, where the default of 4GiB/512GiB remains. The size can be specified by the Kconfig CPU_PT_ROM_MAP_GB option.
Used in the following patch to use ROM3 mapping on AMD platforms.
TEST: Access ROM3 bar at 0xfd00000000 on amd/birman+ using x86_64 TEST: x86_64 still works on qemu/q35.
Change-Id: If669426f2b5ae40dd5c62e17f3a0234783b7d462 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/86580 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Maximilian Brune maximilian.brune@9elements.com --- M src/cpu/x86/64bit/pt.S M src/cpu/x86/64bit/pt1G.S M src/cpu/x86/Kconfig 3 files changed, 31 insertions(+), 13 deletions(-)
Approvals: build bot (Jenkins): Verified Maximilian Brune: Looks good to me, approved
diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S index 1297296..5b10b10 100644 --- a/src/cpu/x86/64bit/pt.S +++ b/src/cpu/x86/64bit/pt.S @@ -20,16 +20,21 @@ .global PML4E .align 4096 PML4E: -.quad _GEN_DIR(PDPT) - -.align 4096 -PDT: /* identity map 2MiB pages */ -.rept 2048 -.quad _GEN_PAGE(0x200000 * ((. - PDT) >> 3)) +/* For every 512GiB generate a pointer to the corresponding PDPT */ +.rept (CONFIG_CPU_PT_ROM_MAP_GB + 511) / 512 +.quad _GEN_DIR(PDPT + 4096 * ((. - PML4E) >> 3)) /* Point to PDPT */ .endr
.align 4096 -PDPT: /* Point to PDT */ -.rept 4 -.quad _GEN_DIR(PDT + 4096 * ((. - PDPT) >> 3)) +PDT: +/* For every 2MiB generate a page entry. In one GiB there are 512 pages. */ +.rept 512 * CONFIG_CPU_PT_ROM_MAP_GB +.quad _GEN_PAGE(0x200000 * ((. - PDT) >> 3)) /* identity map 2MiB page */ +.endr + +.align 4096 +PDPT: +/* For every 1GiB generate a pointer to the corresponding PDT */ +.rept CONFIG_CPU_PT_ROM_MAP_GB +.quad _GEN_DIR(PDT + 4096 * ((. - PDPT) >> 3)) /* Point to PDT */ .endr diff --git a/src/cpu/x86/64bit/pt1G.S b/src/cpu/x86/64bit/pt1G.S index 42cdfb1..b1f4433 100644 --- a/src/cpu/x86/64bit/pt1G.S +++ b/src/cpu/x86/64bit/pt1G.S @@ -20,10 +20,14 @@ .global PML4E .align 4096 PML4E: -.quad _GEN_DIR(PDPT) +/* For every 512GiB generate a pointer to the corresponding PDPT */ +.rept (CONFIG_CPU_PT_ROM_MAP_GB + 511) / 512 +.quad _GEN_DIR(PDPT + 4096 * ((. - PML4E) >> 3)) /* Point to PDPT */ +.endr
.align 4096 -PDPT: /* identity map 1GiB pages * 512 */ -.rept 512 -.quad _GEN_PAGE(0x40000000 * ((. - PDPT) >> 3)) +PDPT: +/* For every 1GiB generate a page entry */ +.rept CONFIG_CPU_PT_ROM_MAP_GB +.quad _GEN_PAGE(0x40000000 * ((. - PDPT) >> 3)) /* identity map 1GiB page */ .endr diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 828c0f9..15c884e 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -159,6 +159,15 @@ Select this option from boards/SoCs that do not support the Page1GB CPUID feature (CPUID.80000001H:EDX.bit26).
+config CPU_PT_ROM_MAP_GB + int + default 4 if NEED_SMALL_2MB_PAGE_TABLES + default 512 + help + GiB of the lower address space to identity map when using x86_64 + page tables in ROM. Higher values require more space in SPI flash. + SoC can overwrite the value if necessary. + config SMM_ASEG bool default n