[coreboot-gerrit] [S] Change in coreboot[master]: soc/amd/mendocino: Add UPD to support USB3 force to gen1 by port

[Patrick Huang (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held.

Patrick Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73916 )

Change subject: soc/amd/mendocino: Add UPD to support USB3 force to gen1 by port
......................................................................

soc/amd/mendocino: Add UPD to support USB3 force to gen1 by port

Add UPD usb3_port_force_gen1 to support USB3 port force to gen1

BUG=b:273841155
BRANCH=skyrim
TEST=Build, verify USB3 port setting to gen1.

Change-Id: Iaa476f56cf10588d7de2203deca4122958c00783
Signed-off-by: Patrick Huang 
---
M src/soc/amd/mendocino/chip.h
M src/soc/amd/mendocino/fsp_m_params.c
2 files changed, 32 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/73916/1

diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h
index 42f27cb..f16f5fd 100644
--- a/src/soc/amd/mendocino/chip.h
+++ b/src/soc/amd/mendocino/chip.h
@@ -13,6 +13,16 @@
 #include <types.h>
 #include <vendorcode/amd/fsp/mendocino/FspUsb.h>

+/* force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1, etc */
+union __packed usb3_force_gen1 {
+		struct {
+			uint8_t xhci0_port0:1;
+			uint8_t xhci1_port0:1;
+			uint8_t xhci1_port1:1;
+		} ports;
+		uint8_t usb3_port_force_gen1_en;
+};
+
 struct soc_amd_mendocino_config {
    struct soc_amd_common_config common_config;
    u8 i2c_scl_reset;
@@ -163,6 +173,10 @@
    /* Set for PCIe optimization w/a and a double confirming on the result of PCIe Signal
       Integrity is highly recommended. */
    uint8_t dxio_tx_vboost_enable;
+
+	/* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */
+	union usb3_force_gen1 usb3_port_force_gen1;
+
 };

#endif /* MENDOCINO_CHIP_H */
diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c
index 8533743..37d4048 100644
--- a/src/soc/amd/mendocino/fsp_m_params.c
+++ b/src/soc/amd/mendocino/fsp_m_params.c
@@ -174,4 +174,6 @@
    fsp_fill_pcie_ddi_descriptors(mcfg);
    fsp_assign_ioapic_upds(mcfg);
    mb_pre_fspm(mcfg);
+
+	mcfg->fch_usb_3_port_force_gen1 = config->usb3_port_force_gen1.usb3_port_force_gen1_en;
 }