[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: add DDR4 mem configuration

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39040 )

Change subject: soc/intel/tigerlake: add DDR4 mem configuration
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Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39040/4/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:

https://review.coreboot.org/c/coreboot/+/39040/4/src/soc/intel/tigerlake/inc... 
PS4, Line 75: spd_addr_table
> I am not 100% sure about this, I need to check with memory team. I will take an AR on this. […]

I don't see a reason why that would be any different than LPDDR4x memory type. You should be able to provide either SpdAddressTable or pointers to actual SPDs. Adding of SPDs to CBFS should not be any different here than what is done on previous platforms.