[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Set Base Addresses for TBT DMA remapping engines

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Sridhar Siricilla, Patrick Rudolph.
Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/55015

to look at the new patch set (#4).

Change subject: soc/intel/alderlake: Set Base Addresses for TBT DMA remapping engines
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soc/intel/alderlake: Set Base Addresses for TBT DMA remapping engines

The patch configures 4KB memory region window for each of the TBT DMA
remapping engine. So, the remap engines map their register set to
the respective 4KB window.

TEST=Verified boot on Brya

Signed-off-by: Sridhar Siricilla 
Change-Id: I669255065d60d73c4bea0eeb732c4114bcc447c0
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 19 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/55015/4