[coreboot-gerrit] Change in coreboot[master]: mb/purism/librem_mini: Fix PCIe clock source mapping in devicetree

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47221 )

Change subject: mb/purism/librem_mini: Fix PCIe clock source mapping in devicetree
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mb/purism/librem_mini: Fix PCIe clock source mapping in devicetree

Correct PCIe clock source mapping in devicetree now that the GPIO
config has been fixed. Move ClkSrcUsage/ClkSrcClkReq registers
under their associated PCIe root ports.

Change-Id: Ibdaba51d971a39a6da6df82652b7420d7324dee5
Signed-off-by: Matt DeVillier 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47221
Tested-by: build bot (Jenkins) 
Reviewed-by: Michael Niewöhner 
---
M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
1 file changed, 6 insertions(+), 16 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
index 918fa0e..becb946 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
@@ -19,22 +19,6 @@

# FSP Silicon (soc/intel/cannonlake/fsp_params.c)

-	# All SRCCLKREQ pins mapped directly
-	register "PcieClkSrcClkReq[0]" = "0"
-	register "PcieClkSrcClkReq[1]" = "1"
-	register "PcieClkSrcClkReq[2]" = "2"
-	register "PcieClkSrcClkReq[3]" = "3"
-	register "PcieClkSrcClkReq[4]" = "4"
-	register "PcieClkSrcClkReq[5]" = "5"
-
-	# Set all SRCCLKREQ pins as free-use
-	register "PcieClkSrcUsage[0]" = "0x80"
-	register "PcieClkSrcUsage[1]" = "0x80"
-	register "PcieClkSrcUsage[2]" = "0x80"
-	register "PcieClkSrcUsage[3]" = "0x80"
-	register "PcieClkSrcUsage[4]" = "0x80"
-	register "PcieClkSrcUsage[5]" = "0x80"
-
    # Misc
    register "AcousticNoiseMitigation" = "1"

@@ -211,6 +195,8 @@
    		register "PcieRpSlotImplemented[7]" = "1"
    		register "PcieRpEnable[7]" = "1"
    		register "PcieRpLtrEnable[7]" = "1"
+			# ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC
+			register "PcieClkSrcUsage[2]" = "0x80"
    		smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther"
    	end
    	device pci 1d.0 off end # PCI Express Port 9
@@ -218,6 +204,8 @@
    		device pci 00.0 on end # x1 (LAN)
    		register "PcieRpSlotImplemented[9]" = "1"
    		register "PcieRpEnable[9]" = "1"
+			register "PcieClkSrcUsage[3]" = "9"
+			register "PcieClkSrcClkReq[3]" = "3"
    	end
    	device pci 1d.2 off end # PCI Express Port 11
    	device pci 1d.3 off end # PCI Express Port 12
@@ -226,6 +214,8 @@
    		register "PcieRpSlotImplemented[12]" = "1"
    		register "PcieRpEnable[12]" = "1"
    		register "PcieRpLtrEnable[12]" = "1"
+			register "PcieClkSrcUsage[1]" = "12"
+			register "PcieClkSrcClkReq[1]" = "1"
    		smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
    	end
    	device pci 1d.5 off end # PCI Express Port 14