Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48264 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters ......................................................................
mb/google/volteer/var/voxel: Update DPTF parameters
remove TCC offset setting in overridetree.cb, use default setting(# TCC of 90) in baseboard.
BUG=b:174547185 BRANCH=volteer TEST=emerge-volteer coreboot
Signed-off-by: Pan Sheng-Liang sheng-liang.pan@quanta.corp-partner.google.com Change-Id: Iaac1fae12ccaa8a623bc2dc3105262918523d440 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48264 Reviewed-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com Reviewed-by: David Wu david_wu@quanta.corp-partner.google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 0 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved David Wu: Looks good to me, but someone else must approve Sheng-Liang Pan: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 9c4aa47..2dd1566 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/tigerlake register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" - register "tcc_offset" = "5" # TCC of 95
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 18,