[coreboot-gerrit] Change in coreboot[master]: Rangeley: Fix incorrect BCLK

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded a new patch set (#11) to the change originally created by [e-mail]. ( https://review.coreboot.org/c/coreboot/+/35348 )

Change subject: Rangeley: Fix incorrect BCLK
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Rangeley: Fix incorrect BCLK

Not all Rangeley SKUs have a fixed 100MHz BCLK.

As per BIOS Writer's Guide, BCLK is available in MSR_FSB_FREQ 0xCD[1:0].
Using fixed BCLK was causing wrong values of core frequencies in _PSS table
for SKUs that do not have BCLK=100MHz.

Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f
Signed-off-by: Hannah Williams 
Signed-off-by: Kyösti Mälkki 
---
M src/cpu/intel/common/fsb.c
M src/cpu/intel/fsp_model_406dx/acpi.c
M src/cpu/intel/fsp_model_406dx/model_406dx.h
3 files changed, 23 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/35348/11