Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46585 )
Change subject: soc/mediatek/mt8192: add dram log prefix ......................................................................
soc/mediatek/mt8192: add dram log prefix
1 Add dram log prefix: [MEM] 2 Print error code when memtest fails.
Signed-off-by: Xi Chen xixi.chen@mediatek.com Change-Id: I6c53c9cecf5996227a3e343fc703b9880d9afeac --- M src/soc/mediatek/mt8192/Kconfig M src/soc/mediatek/mt8192/memory.c 2 files changed, 9 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/46585/1
diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig index 1d1cf7b..2932f25 100644 --- a/src/soc/mediatek/mt8192/Kconfig +++ b/src/soc/mediatek/mt8192/Kconfig @@ -32,10 +32,14 @@ bool default n help - This options enables DRAM calibration with multiple frequencies (low, + This option enables DRAM calibration with multiple frequencies (low, medium and high) for DVFS feature.
config MEMORY_TEST bool default y + help + This option will do memory basic compare test to verify the dram read + or write is as expect. + endif diff --git a/src/soc/mediatek/mt8192/memory.c b/src/soc/mediatek/mt8192/memory.c old mode 100644 new mode 100755 index b5363b0..19a702d --- a/src/soc/mediatek/mt8192/memory.c +++ b/src/soc/mediatek/mt8192/memory.c @@ -15,13 +15,13 @@ const struct ddr_base_info *ddr_info = &dparam->ddr_info;
for (u8 rank = RANK_0; rank < ddr_info->support_ranks; rank++) { - int i = complex_mem_test(addr, 0x2000); + int result = complex_mem_test(addr, 0x2000);
printk(BIOS_DEBUG, "[MEM] complex R/W mem test %s\n", - (i == 0) ? "pass" : "fail"); + (result == CB_SUCCESS) ? "pass" : "fail");
- if (i != 0) { - printk(BIOS_ERR, "DRAM memory test failed\n"); + if (result != 0) { + printk(BIOS_ERR, "[MEM] DRAM memory test failed: %d\n", result); return -1; }