[coreboot-gerrit] Change in ...coreboot[master]: soc/intel: Provide SPD manufacturer ID and module type to SMBIOS

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33379 )

Change subject: soc/intel: Provide SPD manufacturer ID and module type to SMBIOS
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Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/33379/1/src/soc/intel/apollolake/meminit_uti... 
File src/soc/intel/apollolake/meminit_util_apl.c:

https://review.coreboot.org/#/c/33379/1/src/soc/intel/apollolake/meminit_uti... 
PS1, Line 98: 				0);
> I don't believe there are APL designs with actual DIMM and SPD, they should all be LPDDR.

I think most of chrome project use the on-board ram with SPD file which we can read from ROM directly. Is Sarien the first one use the switchable RAM? If with SPD file we can easily do it within coreboot. With dynamic ram will be a duplicate work in FSP and coreboot.