[coreboot-gerrit] Change in ...coreboot[master]: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake

[Bora Guvendik (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/33818

to look at the new patch set (#4).

Change subject: vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake
......................................................................

vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for Cannonlake

Update FSP header files with 7.0.64.40 version for Cannonlake platform,
the following changes were made,
Silicon Init UPD:
        1. Add UPD to disable Heci1.
        2. Add CD clock selections of 675MHz.
        3. Add UPD to program GT Chicken bits.
        4. Add various xHCI USB related UPDs.
        5. Teton Glacier Cycle Router UPD deprecated.
        6. CdynmaxClampEnable is enabled by default now.
        7. Add UPDs for C3 Cstate Demotion.
Memory Init UPD:
    1. Add GDXC configuration options.
    2. Remove some internal graphics memory selections.
    3. Remove Fixed mid option for SaGv.
    4. Add DualDimm per channel board type.
    5. Add UPD for DDR4 mixed U-DIMM 2DPC Limitation.
    6. Add UPD to skip DDR4 refresh.
    7. Add UPD for Lpddr Dram Odt.

Change-Id: If71e5fb8ae9f48a232b6b507e19145e1c06c2e83
Signed-off-by: Bora Guvendik 
---
M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
2 files changed, 176 insertions(+), 69 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/33818/4