[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add macros and SPD information for DDR4

[Furquan Shaikh (Code Review)]

Hello build bot (Jenkins), Tim Wawrzynczak, Varun Joshi, Varun Joshi, Patrick Rudolph, EricR Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39866

to look at the new patch set (#13).

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

soc/intel/tigerlake: Add macros and SPD information for DDR4

This change adds new memory topologies (SODIMM, MIXED) that are
supported by DDR4 and macros required for DDR4 support.

Memory initialization support for DDR4 will be added in a follow-up
change.

Signed-off-by: Furquan Shaikh 
Change-Id: I4b565c3d71bbf437da64ac29597cc19e58f1b98a
---
M src/soc/intel/tigerlake/include/soc/meminit.h
1 file changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39866/13