Sumeet R Pawnikar (sumeet.r.pawnikar@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17921
-gerrit
commit 45713217e922ea4778a1b40ff3a808f0c2797e7b Author: Sumeet Pawnikar sumeet.r.pawnikar@intel.com Date: Tue Dec 20 01:39:26 2016 +0530
mainboard/google/chell: Set target offset value to 10 degree C
With the default target offset value as 0 and target temperature Tjmax value as 100 degree C, Pcode firmware starts taking prochot action at 100 degree C [Tjmax-Offset]. But before Pcode firmware starts prochot action at 100 degree C, device is getting shutdown at 99 degree C due to DPTF critical CPU temperature. This patch sets target offset value to 10 degree C for thermal throttle activation and to prevent this kind of thermal shutdown.
BUG=chrome-os-partner:59397 BRANCH=None. TEST=Built, booted on skylake and verified target offset value.
Change-Id: I0811ef481a4b3ce4bd6ef24f2aa8160f44f9c990 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- src/mainboard/google/chell/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index 34250d3..2ffaec6 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -183,6 +183,8 @@ chip soc/intel/skylake # PL2 override 15W register "tdp_pl2_override" = "15"
+ register "tcc_offset" = "10" # TCC of 90C + # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1"