Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40648 )
Change subject: soc/intel/tigerlake: Print HPR_CAUSE0 register ......................................................................
Patch Set 7:
(5 comments)
Patch Set 6:
Would you mind splitting out the elog.c change into a different CL?
Done
https://review.coreboot.org/c/coreboot/+/40648/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40648/1//COMMIT_MSG@10 PS1, Line 10: HPR_CAUSE0 to understand the causes of host reset
Please add a dot/period at the end of sentences.
Done
https://review.coreboot.org/c/coreboot/+/40648/3/src/include/elog.h File src/include/elog.h:
https://review.coreboot.org/c/coreboot/+/40648/3/src/include/elog.h@198 PS3, Line 198: /* ME-Initiated Host Reset */ : #define ELOG_TYPE_MI_HRPD 0xb3 : #define ELOG_TYPE_MI_HRPC 0xb4 : #define ELOG_TYPE_MI_HR 0xb5
Should we create separate patch for this header change? […]
OK. I will create a separate patch for header change
https://review.coreboot.org/c/coreboot/+/40648/5/src/soc/intel/tigerlake/elo... File src/soc/intel/tigerlake/elog.c:
https://review.coreboot.org/c/coreboot/+/40648/5/src/soc/intel/tigerlake/elo... PS5, Line 65: downi
down
Done
https://review.coreboot.org/c/coreboot/+/40648/5/src/soc/intel/tigerlake/elo... PS5, Line 67: ELOG_TYPE_MI_HRPD
Where are these ELOG_TYPE_MI_* defined? I don't see them... […]
Done. A separate patch is created for header file. will submit mosys CL once the changes are merged.
https://review.coreboot.org/c/coreboot/+/40648/2/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/40648/2/src/soc/intel/tigerlake/inc... PS2, Line 123:
I think it may be useful to call out the CSME-initiated bits here. […]
Done