Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38737 )
Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
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Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/rom...
File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/rom...
PS1, Line 137: m_cfg->TcssItbtPcie3En = 1;
Why does the information need to be in two places?
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf
Gerrit-Change-Number: 38737
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Gerrit-Comment-Date: Fri, 07 Feb 2020 12:22:24 +0000
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