[coreboot-gerrit] Change in coreboot[master]: riscv: add smp support for exception handle

[Xiang Wang (Code Review)]

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33656 )

Change subject: riscv: add smp support for exception handle
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Patch Set 3:
> Patch Set 3:
>
> Thanks Xiang,
>
> Did you test this on both hardware and qemu?

This code does not affect the current code. To test this code, you need to add a test case. I did not do this part of the test.