Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )
Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode ......................................................................
Patch Set 15:
(5 comments)
https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG@9 PS7, Line 9: Added change to select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED : is selected in Tigerlake soc Kconfig.
That sounds okay. […]
Done
https://review.coreboot.org/c/coreboot/+/47259/10//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47259/10//COMMIT_MSG@14 PS10, Line 14: 171601324
This should be b:171601324
Done
https://review.coreboot.org/c/coreboot/+/47259/10//COMMIT_MSG@15 PS10, Line 15: Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.
BRANCH=volteer
Done
https://review.coreboot.org/c/coreboot/+/47259/14//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47259/14//COMMIT_MSG@9 PS14, Line 9: IA32_PQR_ASSOC (0xC8F) MSR's Bits[32:33] are used for mask selection : when Kconfig COS_MAPPED_TO_MSB is selected. In cpu/Kconfig, if : INTEL_CAR_NEM_ENHANCED is selected, in tigerlake/Kconfig, selecting : COS_MAPPED_TO_MSB to ensure Bits[32:33] are used for mask selection.
Can you please address this as well?
Done
https://review.coreboot.org/c/coreboot/+/47259/13/src/soc/intel/tigerlake/Kc... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/47259/13/src/soc/intel/tigerlake/Kc... PS13, Line 26: USE_CAR_NEM_ENHANCED_V1
I got your point now. I will update.
Done