Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47860 )
Change subject: soc/intel/tigerlake: Refactor TCSS port mux config ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47860/1/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/47860/1/src/soc/intel/tigerlake/fsp... PS1, Line 135: TGL_LP_GPIO_ID Can you please add a comment why this is required to be set even if there is no bias_control information being provided?
https://review.coreboot.org/c/coreboot/+/47860/1/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/early_tcss.h:
https://review.coreboot.org/c/coreboot/+/47860/1/src/soc/intel/tigerlake/inc... PS1, Line 102: TGL_LP_GPIO_ID Can you please add a comment here that this is expected to be set by FSP and it represents the GPIO chipset ID for LP.
(This is another example of how FSP is leaking its assumptions into external components).