[coreboot-gerrit] Change in coreboot[master]: google/fizz: disable Apex power enable in S3 sleep

[Zhongze Hu (Code Review)]

Zhongze Hu has uploaded this change for review. ( https://review.coreboot.org/25910

Change subject: google/fizz: disable Apex power enable in S3 sleep
......................................................................

google/fizz: disable Apex power enable in S3 sleep

CFM daughter card shares the 3.3V rail with SSD and is enabled by
3 GPIOs GPP_B20, GPP_C8 and GPP_C9. When entering S3 power state,
these GPIOs will back bios the 3.3V rail to 1.5V, which sometimes
casues SSD fail to resume. This CL disables these GPIOs in the
sleep path.

BUG=b:77931014
BRANCH=None
TEST=Compiles successfully, will test on a device and update

Change-Id: Ieaa798bcc90dbac4a9a4ee5b43b7a851358ee3c4
Signed-off-by: Zhongze Hu 
---
M src/mainboard/google/fizz/gpio.h
M src/mainboard/google/fizz/smihandler.c
2 files changed, 23 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/25910/1

diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h
index 9a94af4..a750edc 100644
--- a/src/mainboard/google/fizz/gpio.h
+++ b/src/mainboard/google/fizz/gpio.h
@@ -42,6 +42,11 @@
 #define GPIO_OEM_ID2		GPP_D11
 #define GPIO_OEM_ID3		GPP_D12

+/* CFM APEX chips enable GPIOs */
+#define GPIO_APEX_VCOM_EN	GPP_B20
+#define GPIO_APEX0_VR_EN	GPP_C8
+#define GPIO_APEX1_VR_EN	GPP_C9
+
 #ifndef __ACPI__
 /* Pad configuration in ramstage */
 /* Leave eSPI pins untouched from default settings */
diff --git a/src/mainboard/google/fizz/smihandler.c b/src/mainboard/google/fizz/smihandler.c
index 5f05b2e..8d5fd77 100644
--- a/src/mainboard/google/fizz/smihandler.c
+++ b/src/mainboard/google/fizz/smihandler.c
@@ -24,10 +24,28 @@
    chromeec_smi_process_events();
 }

+static void mainboard_gpio_smi_sleep(u8 slp_typ)
+{
+	int i;
+	
+	gpio_t active_high_signals[] = {
+		GPIO_APEX_VCOM_EN,
+		GPIO_APEX0_VR_EN,
+		GPIO_APEX1_VR_EN,
+	};
+
+	for (i = 0; i < ARRAY_SIZE(active_high_signals); i++)
+		gpio_set(active_high_signals[i], 0);
+}
+
 void mainboard_smi_sleep(u8 slp_typ)
 {
    chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
    		MAINBOARD_EC_S5_WAKE_EVENTS);
+
+	/* Disable the Apex enable signals on S3 state. */
+	if (slp_typ == ACPI_S3)
+		mainboard_gpio_smi_sleep(slp_typ);
 }

int mainboard_smi_apmc(u8 apmc)