Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41534 )
Change subject: soc/intel/jasperlake: Use coreboot lock down config ......................................................................
soc/intel/jasperlake: Use coreboot lock down config
Allow lockdown configuration from using CHIPSET_LOCKDOWN_COREBOOT config.
TEST=Build and boot waddledoo board
Change-Id: I3abaa737580ef45b98cabfa23edd84162037dd70 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 13 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/41534/1
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 45162f9..eafc374 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -7,6 +7,7 @@ #include <intelblocks/lpss.h> #include <intelblocks/mp_init.h> #include <intelblocks/xdci.h> +#include <intelpch/lockdown.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> @@ -105,8 +106,18 @@ params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; }
- /* Unlock upper 8 bytes of RTC RAM */ - params->RtcMemoryLock = 0; + /* Chipset Lockdown */ + if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { + params->PchLockDownGlobalSmi = 0; + params->PchLockDownBiosInterface = 0; + params->PchUnlockGpioPads = 1; + params->RtcMemoryLock = 0; + } else { + params->PchLockDownGlobalSmi = 1; + params->PchLockDownBiosInterface = 1; + params->PchUnlockGpioPads = 0; + params->RtcMemoryLock = 1; + }
/* Enable End of Post in PEI phase */ params->EndOfPostMessage = EOP_PEI;