[coreboot-gerrit] Change in coreboot[master]: security/intel/stm: Add STM support

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33234 )

Change subject: security/intel/stm: Add STM support
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Patch Set 57:

(1 comment)

Sorry for bugging you after merge btw. I do understand that you
wanted to avoid breakage by squashing commits, however I guess
that you didn't get the usual heads up because of the big commit
with `security/intel/` prefix.

If you have even trouble splitting commits again, feel free to
ask on the mailing list or IRC.

https://review.coreboot.org/c/coreboot/+/33234/57/src/cpu/x86/smm/smm_module... 
File src/cpu/x86/smm/smm_module_loader.c:

https://review.coreboot.org/c/coreboot/+/33234/57/src/cpu/x86/smm/smm_module... 
PS57, Line 365: 		base += size - CONFIG_MSEG_SIZE;     // take out the mseg
> MSEG, aka monitor segment, is where the STM is loaded.  It is normally at the top of the TSEG, and in coreboot the MSEG is located in the region above where the SMI handler is located.  It was not added in this diagram because the function is focused on the SMI handler (aka SMM module)

If that is the case, shouldn't the caller take care of subtracting MSEG?