EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46868 )
Change subject: mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku ......................................................................
mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku
LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition.
If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.
BUG=b:171478764 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I3a04320b0e2441dce540a5afdc461f12de45c41b --- M src/mainboard/google/octopus/variants/fleex/overridetree.cb M src/mainboard/google/octopus/variants/fleex/variant.c 2 files changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/46868/1
diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index 679b101..cf1792b 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -84,6 +84,8 @@ }, }"
+ register "disable_xhci_lfps_pm" = "0" + device domain 0 on device pci 16.0 on chip drivers/i2c/hid diff --git a/src/mainboard/google/octopus/variants/fleex/variant.c b/src/mainboard/google/octopus/variants/fleex/variant.c index 522faa9..ab75602 100644 --- a/src/mainboard/google/octopus/variants/fleex/variant.c +++ b/src/mainboard/google/octopus/variants/fleex/variant.c @@ -4,6 +4,7 @@ #include <baseboard/variants.h> #include <ec/google/chromeec/ec.h> #include <sar.h> +#include <soc/intel/apollolake/chip.h>
#define MIN_LTE_SKU 4
@@ -31,3 +32,13 @@
return filename; } + +void variant_update_devtree(struct device *dev) +{ + struct soc_intel_apollolake_config *cfg = NULL; + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; + if (cfg != NULL && (cfg->disable_xhci_lfps_pm != 1)) { + if (is_lte_sku) + cfg->disable_xhci_lfps_pm = 1; + } +}