[coreboot-gerrit] Change in coreboot[master]: mb/google/hatch/var/jinlon: Configure GPP_E0 as output

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39144 )

Change subject: mb/google/hatch/var/jinlon: Configure GPP_E0 as output
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mb/google/hatch/var/jinlon: Configure GPP_E0 as output

Configure GPP_E0 as output for view angle management

Change-Id: Iad640eed855b47e365da55fa994c6a3c4c38caf9
Signed-off-by: Rajat Jain .
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39144
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Tim Wawrzynczak 
---
M src/mainboard/google/hatch/variants/jinlon/gpio.c
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c
index 2bf97b1..c584d94 100644
--- a/src/mainboard/google/hatch/variants/jinlon/gpio.c
+++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c
@@ -31,6 +31,8 @@
     * using this pin, expose this pin to driver.
     */
    PAD_CFG_GPO(GPP_C15, 1, DEEP),
+	/* E0 : View Angle Management */
+	PAD_CFG_GPO(GPP_E0, 0, DEEP),
    /* F3  : MEM_STRAP_3 */
    PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
    /* F10 : MEM_STRAP_2 */