William Wei has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42677 )
Change subject: soc/intel/tigerlake: Change pmc_set_acpi_mode() run after BS_DEV_INIT. ......................................................................
soc/intel/tigerlake: Change pmc_set_acpi_mode() run after BS_DEV_INIT.
pmc_set_acpi_mode() should run after Chrome EC deal with all host event bits, like SMI mask (otherwise the FAFT firmware_FWScreenCloseLid test will fail.)
BUG=b:153249055 TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage Change the GBB flag to 0x140 then check SMI mask during depthcharge phase, make sure it's 0x0000000000000001.
Signed-off-by: William Wei wenxu.wei@bitland.corp-partner.google.com Change-Id: Icfff5cc5550f23938343e4d26ef76093bb9cf7c3 --- M src/soc/intel/tigerlake/pmc.c 1 file changed, 25 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/42677/1
diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 4d89870..a65aeb8 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -7,6 +7,7 @@ */
#include <acpi/acpigen.h> +#include <bootstate.h> #include <console/console.h> #include <device/mmio.h> #include <device/device.h> @@ -77,8 +78,6 @@ pmc_set_power_failure_state(true); pmc_gpe_init();
- pmc_set_acpi_mode(); - config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); config_deep_sx(config->deep_sx_config); @@ -142,6 +141,30 @@ return child; }
+static void soc_acpi_mode_init(void *unused) +{ + /* + * PMC initialization happens earlier for this SoC because FSP-Silicon + * init hides PMC from PCI bus. However, pmc_set_acpi_mode, which + * disables ACPI mode doesn't need to happen that early and can be + * delayed till typical BS_DEV_INIT. This ensures that ACPI mode + * disabling happens the same way for all SoCs and hence the ordering of + * events is the same. + * + * This is important to ensure that the ordering does not break the + * assumptions of any other drivers (e.g. ChromeEC) which could be + * taking different actions based on disabling of ACPI (e.g. flushing of + * all EC hostevent bits). + * + * P.S.: This cannot be done as part of pmc_soc_init as PMC device is + * hidden and hence the PMC driver never gets enumerated and so init is + * not called for it. + */ + pmc_set_acpi_mode(); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_acpi_mode_init, NULL); + struct device_operations pmc_ops = { .read_resources = soc_pmc_read_resources, .set_resources = noop_set_resources,