Hannah Williams (hannah.williams@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13122
-gerrit
commit fa73f6bf3182d3551436beda21660e0d5b6f8907 Author: Divagar Mohandass divagar.mohandass@intel.com Date: Tue Sep 8 15:03:45 2015 +0530
intel/strago: Clean up DDR configuration.
This change includes following changes: - Clean up the DDR configuration and flow. - Removing support for non LPDDR3 boards. - Supporting only LPDDR3 and PMIC config.
TEST=Build/flash CB and boot the platform to OS.
Change-Id: I8369443da728a4c07e0c1a82040d94034c3542da Signed-off-by: Divagar Mohandass divagar.mohandass@intel.com Original-Reviewed-on: https://chromium-review.googlesource.com/297941 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org Original-Reviewed-by: Jenny Tc jenny.tc@intel.com Signed-off-by: Hannah Williams hannah.williams@intel.com --- src/mainboard/intel/strago/Kconfig | 6 -- src/mainboard/intel/strago/Makefile.inc | 2 - src/mainboard/intel/strago/ramstage.c | 6 +- src/mainboard/intel/strago/romstage.c | 26 +---- src/mainboard/intel/strago/smihandler.c | 8 +- src/mainboard/intel/strago/spd/Makefile.inc | 38 ------- .../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 32 ------ ...nix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex | 32 ------ .../spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex | 32 ------ src/mainboard/intel/strago/spd/spd.c | 116 --------------------- 10 files changed, 6 insertions(+), 292 deletions(-)
diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 204534a..f23a86c 100755 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -21,12 +21,6 @@ config CHROMEOS select VBOOT_DYNAMIC_WORK_BUFFER select VIRTUAL_DEV_SWITCH
-config DISPLAY_SPD_DATA - bool "Display Memory Serial Presence Detect Data" - default n - help - When enabled displays the memory configuration data. - config DYNAMIC_VNN_SUPPORT bool "Enables support for Dynamic VNN" default n diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index d53cd84..9c21bed 100755 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -14,8 +14,6 @@ ## GNU General Public License for more details. ##
-subdirs-y += spd - romstage-y += boardid.c romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c diff --git a/src/mainboard/intel/strago/ramstage.c b/src/mainboard/intel/strago/ramstage.c index c5cff68..a05cd90 100644 --- a/src/mainboard/intel/strago/ramstage.c +++ b/src/mainboard/intel/strago/ramstage.c @@ -19,8 +19,6 @@
void mainboard_silicon_init_params(SILICON_INIT_UPD *params) { - if (board_id() == BOARD_BCRD2) { - params->ChvSvidConfig = SVID_PMIC_CONFIG; - params->PMIC_I2CBus = BCRD2_PMIC_I2C_BUS; - } + params->ChvSvidConfig = SVID_PMIC_CONFIG; + params->PMIC_I2CBus = BCRD2_PMIC_I2C_BUS; } diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c index e582b56..56ab9a7 100755 --- a/src/mainboard/intel/strago/romstage.c +++ b/src/mainboard/intel/strago/romstage.c @@ -25,32 +25,8 @@ #include "onboard.h" #include <boardid.h>
-/* All FSP specific code goes in this block */ -void mainboard_romstage_entry(struct romstage_params *rp) -{ - struct pei_data *ps = rp->pei_data; - - mainboard_fill_spd_data(ps); - - /* Call back into chipset code with platform values updated. */ - romstage_common(rp); -} - void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { - int id; - id = board_id(); - if (id == BOARD_BCRD2) { - memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; - memory_params->PcdDvfsEnable = 0; - } else { - memory_params->PcdMemoryTypeEnable = MEM_DDR3; - memory_params->PcdMemorySpdPtr = - (u32)params->pei_data->spd_data_ch0; - memory_params->PcdMemChannel0Config = - params->pei_data->spd_ch0_config; - memory_params->PcdMemChannel1Config = - params->pei_data->spd_ch1_config; - } + memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; } diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index b465e3a..0f77bf3 100755 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -139,11 +139,9 @@ void mainboard_smi_sleep(uint8_t slp_typ) while (google_chromeec_get_event() != 0) ;
- if (smm_get_gnvs()->bdid == BOARD_DVT) { - /* Set LPC lines to low power in S3/S5. */ - if ((slp_typ == SLEEP_STATE_S3) || (slp_typ == SLEEP_STATE_S5)) - lpc_set_low_power(); - } + /* Set LPC lines to low power in S3/S5. */ + if ((slp_typ == SLEEP_STATE_S3) || (slp_typ == SLEEP_STATE_S5)) + lpc_set_low_power(); #endif }
diff --git a/src/mainboard/intel/strago/spd/Makefile.inc b/src/mainboard/intel/strago/spd/Makefile.inc deleted file mode 100755 index 440735c..0000000 --- a/src/mainboard/intel/strago/spd/Makefile.inc +++ /dev/null @@ -1,38 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -romstage-y += spd.c - -SPD_BIN = $(obj)/spd.bin - -SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 -SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR -SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 -SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex deleted file mode 100755 index ff4fd29..0000000 --- a/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 12 0b 03 04 19 02 02 -03 52 01 08 0a 00 fe 00 -69 78 69 3c 69 11 18 81 -20 08 3c 3c 01 40 83 01 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0f 11 62 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 ad 01 -00 00 00 00 00 00 ff ab -48 4d 54 34 32 35 53 36 -41 46 52 36 41 2d 50 42 -20 20 4e 30 80 ad 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff diff --git a/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex deleted file mode 100755 index fdd1a43..0000000 --- a/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 13 0B 03 04 19 02 02 -03 52 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 -20 08 3C 3C 01 40 83 01 -00 00 00 00 00 00 00 00 -00 88 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0F 11 62 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 AD 01 -00 00 00 00 00 00 C9 C0 -48 4D 54 34 32 35 53 36 -43 46 52 36 41 2D 50 42 -20 20 4E 30 80 AD 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF diff --git a/src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex deleted file mode 100755 index e0b0ac5..0000000 --- a/src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 12 0B 03 04 19 02 02 -03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 -20 08 3C 3C 01 40 83 05 -00 00 00 00 00 00 00 00 -88 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 CE 01 -00 00 00 00 00 00 6C F9 -4D 34 37 31 42 35 36 37 -34 51 48 30 2D 59 4B 30 -20 20 00 00 80 CE 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/strago/spd/spd.c b/src/mainboard/intel/strago/spd/spd.c deleted file mode 100755 index a711049..0000000 --- a/src/mainboard/intel/strago/spd/spd.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbfs.h> -#include <console/console.h> -#include <lib.h> -#include <soc/gpio.h> -#include <soc/romstage.h> -#include <string.h> - -#define SPD_SIZE 256 -#define SATA_GP3_PAD_CFG0 0x5828 -#define I2C3_SCL_PAD_CFG0 0x5438 -#define MF_PLT_CLK1_PAD_CFG0 0x4410 -#define I2C3_SDA_PAD_CFG0 0x5420 - -/* - * 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz - * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz - * 0b0010- 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz - * 0b0011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz - */ -static const uint32_t dual_channel_config = (1 << 0); - -static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) -{ - int ram_id = 0; - ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, SATA_GP3_PAD_CFG0) << 0; - ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SCL_PAD_CFG0) << 1; - ram_id |= get_gpio(COMMUNITY_GPSOUTHEAST_BASE, MF_PLT_CLK1_PAD_CFG0) - << 2; - ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SDA_PAD_CFG0) << 3; - - /* - * There are only 2 SPDs supported on Cyan Board: - * Samsung 4G:0000 & Hynix 2G:0011 - */ - - /* - * RAMID0 on the first boot does not read the correct value,so checking - * bit 1 is enough as WA - */ - if (ram_id > 0) - ram_id = 3; - printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); - - if (ram_id >= total_spds) - return NULL; - - /* Single channel configs */ - if (dual_channel_config & (1 << ram_id)) - *dual = 1; - - return &spd_file_content[SPD_SIZE * ram_id]; -} - -/* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *ps) -{ - char *spd_file; - size_t spd_file_len; - void *spd_content; - int dual_channel = 0; - - /* Find the SPD data in CBFS. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < SPD_SIZE) - die("Missing SPD data."); - - /* - * Both channels are always present in SPD data. Always use matched - * DIMMs so use the same SPD data for each DIMM. - */ - spd_content = get_spd_pointer(spd_file, - spd_file_len / SPD_SIZE, - &dual_channel); - if (IS_ENABLED(CONFIG_DISPLAY_SPD_DATA) && spd_content != NULL) { - printk(BIOS_DEBUG, "SPD Data:\n"); - hexdump(spd_content, SPD_SIZE); - printk(BIOS_DEBUG, "\n"); - } - - /* - * Set SPD and memory configuration: - * Memory type: 0=DimmInstalled, - * 1=SolderDownMemory, - * 2=DimmDisabled - */ - if (spd_content != NULL) { - ps->spd_data_ch0 = spd_content; - ps->spd_ch0_config = 1; - if (dual_channel) { - ps->spd_data_ch1 = spd_content; - ps->spd_ch1_config = 1; - } else { - ps->spd_ch1_config = 2; - } - } -}