[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: revert renaming of CONFIG_MAX_PCIE_CLOCKS

[Rizwan Qureshi (Code Review)]

Attention is currently required from: Patrick Rudolph.
Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/52194

to look at the new patch set (#3).

Change subject: soc/intel/alderlake: revert renaming of CONFIG_MAX_PCIE_CLOCKS
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soc/intel/alderlake: revert renaming of CONFIG_MAX_PCIE_CLOCKS

CONFIG_MAX_PCIE_CLOCKS was renamed to MAX_PCIE_CLOCK_SRC in alderlake. However, this config
is being used in common/block/pcie/rtd3 to validate clksrc range.

Signed-off-by: Rizwan Qureshi 
Change-Id: I747c94331b68c4ec0b6b5a04149856a4bb384829
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/romstage/fsp_params.c
3 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/52194/3