[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Align chipset.cb with pci_devs.h

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48153 )

Change subject: soc/intel/alderlake: Align chipset.cb with pci_devs.h
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Patch Set 4: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/48153/2/src/soc/intel/alderlake/chi... 
File src/soc/intel/alderlake/chipset.cb:

https://review.coreboot.org/c/coreboot/+/48153/2/src/soc/intel/alderlake/chi... 
PS2, Line 16: tcss_xhci off end
            : 		device pci 0d.1 alias tcss_xdci off end
            : 		device pci 0d.2 alias tcss_dma0 off end
            : 		device pci 0d.3 alias tcss_dma1 off end
> coreboot/src/soc/intel/alderlake/include/soc/pci_devs.h, I follow this header file. […]

That's fine. FYI, it's from the old southbridge (slow I/O) / northbridge  (fast I/O) distinction. Sometimes the core+uncore is still called the north complex, and the PCH is the south complex.