Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Saurabh Mishra, Subrata Banik, Wonkyu Kim.
Hello Bora Guvendik, Jamie Ryu, Jérémy Compostella, Saurabh Mishra, Subrata Banik, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83981?usp=email
to look at the new patch set (#4).
Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID and vw mapping fix ......................................................................
soc/intel/common/gpio: support 16-bit CPU Port ID and vw mapping fix
Add Kconfig: SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID. Change cpu_port field to 16-bit width if the Kconfig is set. Add specific virtual wire mapping structure for: - First pad group does not starts with bit position 0. - vw_index and position are not continuous in between groups within a community.
BUG= TEST=boot to OS and use iotools to read the registers that use 16-bit port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group ID field.
Signed-off-by: Cliff Huang cliff.huang@intel.com Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d --- M src/soc/intel/common/block/gpio/Kconfig M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h 3 files changed, 52 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/83981/4