build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 )
Change subject: riscv: update misaligned memory access exception handling ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/#/c/27972/1/src/arch/riscv/misaligend.c File src/arch/riscv/misaligend.c:
https://review.coreboot.org/#/c/27972/1/src/arch/riscv/misaligend.c@176 PS1, Line 176: int regnum = ((insn >> match->reg_shift) & match->reg_mask) + \ Avoid unnecessary line continuations
https://review.coreboot.org/#/c/27972/1/src/arch/riscv/misaligend.c@185 PS1, Line 185: buff.b[i] = mprv_read_u8((uint8_t *) \ Avoid unnecessary line continuations
https://review.coreboot.org/#/c/27972/1/src/arch/riscv/misaligend.c@242 PS1, Line 242: mprv_write_u8((uint8_t *)(tf->badvaddr + i), \ Avoid unnecessary line continuations
https://review.coreboot.org/#/c/27972/1/src/arch/riscv/trap_handler.c File src/arch/riscv/trap_handler.c:
https://review.coreboot.org/#/c/27972/1/src/arch/riscv/trap_handler.c@191 PS1, Line 191: write_csr(sepc, read_csr(mepc)); 'sepc' may be misspelled - perhaps 'spec'?