[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/apollolake: Override GLK usb clock gating register

[John Zhao (Code Review)]

Hello John Zhao,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/30918

to review the following change.

Change subject: soc/intel/apollolake: Override GLK usb clock gating register
......................................................................

soc/intel/apollolake: Override GLK usb clock gating register

It was observed system suspend/resume failure while running
RunInDozingStress. Apply correct GLK usb clock gating register
value to mitigate the failure.

BRANCH=octopus
BUG=b:120526309
TEST=Verified GLK clock gating register value after booting
to kernel.

Change-Id: I50fb16f5ab0e28e79f71c7f0f8e75ac8791c0747
Signed-off-by: John Zhao 
---
M src/soc/intel/apollolake/chip.c
1 file changed, 19 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/30918/1

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index b38265f..ad98f5f 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -60,6 +60,8 @@
 #define DRD_MODE_MASK           (1 << 29)
 #define DRD_MODE_HOST           (1 << 29)

+#define CFG_XHCLKGTEN		0x8650
+
 const char *soc_acpi_name(const struct device *dev)
 {
    if (dev->path.type == DEVICE_PATH_DOMAIN)
@@ -733,6 +735,11 @@

void platform_fsp_notify_status(enum fsp_notify_phase phase)
 {
+	uint32_t *cfg;
+	const struct resource *res;
+	uint32_t reg;
+	struct device *xhci_dev = PCH_DEV_XHCI;
+
    if (phase == END_OF_FIRMWARE) {

/*
@@ -758,6 +765,18 @@
    	 */
    	if (check_xdci_enable())
    		configure_xhci_host_mode_port0();
+
+		/*
+		 * Override GLK clock gating register(XHCLKGTEN) to mitigate
+		 * usb device suspend and resume failure.
+		 */
+		if (IS_ENABLED(CONFIG_SOC_INTEL_GLK))
+		{
+			res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0);
+			cfg = (void *)(uintptr_t)(res->base + CFG_XHCLKGTEN);
+			reg = 0x0FCE6E5F;
+			write32(cfg, reg);
+		}
    }
 }