Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37303 )
Change subject: soc/intel/broadwell_de: Re-read SPD on CRC error
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Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwell...
File src/soc/intel/fsp_broadwell_de/romstage/memory.c:
https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwell...
PS2, Line 58: = SPD_STATUS_OK
This is not strictly needed here because res will be assigned a value in line 65 and noone needs it before this line. But it's up to you.
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Gerrit-Project: coreboot
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Gerrit-Change-Number: 37303
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