Eran Mitrani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78449?usp=email )
Change subject: mb/google/rex/variants/deku: Add I2C config ......................................................................
mb/google/rex/variants/deku: Add I2C config
BUG=b:305793886 TEST=None yet
Signed-off-by: Eran Mitrani mitrani@google.com Change-Id: I496e236531b2b59b320c77c36f542f4fa80a51a1 --- M src/mainboard/google/rex/variants/deku/overridetree.cb 1 file changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/78449/1
diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb index b68840f..293e6d6 100644 --- a/src/mainboard/google/rex/variants/deku/overridetree.cb +++ b/src/mainboard/google/rex/variants/deku/overridetree.cb @@ -1,4 +1,40 @@ chip soc/intel/meteorlake + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C4 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[4] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + device domain 0 on + device ref i2c4 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E03_IRQ)" + device i2c 50 on end + end + end end + end