[coreboot-gerrit] Change in coreboot[master]: soc/amd/common/lpc: Add decode disable function

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35270 )

Change subject: soc/amd/common/lpc: Add decode disable function
......................................................................

soc/amd/common/lpc: Add decode disable function

It is already trivial to set D14F3x44 to 0, but add a function to wipe
both that and the settings in D14F3x48, along with x48's associated
addresses.

Change-Id: Ibec25562b2a1568681aea7caf86f00094c436a50
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/common/block/include/amdblocks/lpc.h
M src/soc/amd/common/block/lpc/lpc_util.c
2 files changed, 17 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/35270/1

diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index 6b6745d..0f4f616 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -68,6 +68,7 @@
 #define   DECODE_IO_PORT_ENABLE2	BIT(18)
 #define   DECODE_IO_PORT_ENABLE1	BIT(17)
 #define   DECODE_IO_PORT_ENABLE0	BIT(16)
+#define   LPC_SYNC_TIMEOUT_COUNT_MASK	0xff
 #define   LPC_SYNC_TIMEOUT_COUNT_ENABLE	BIT(7)
 #define   LPC_DECODE_RTC_IO_ENABLE	BIT(6)
 #define   DECODE_MEM_PORT_ENABLE0	BIT(5)
@@ -134,6 +135,7 @@
 #define   PREFETCH_EN_SPI_FROM_HOST	BIT(0)
 #define   T_START_ENH			BIT(3)

+void lpc_disable_decodes(void);
 /* LPC is typically enabled very early, but this function is last opportunity */
 void soc_late_lpc_bridge_enable(void);
 void lpc_enable_port80(void);
diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index 008d14c..485eeda 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -170,6 +170,21 @@
    pci_write_config32(_LPCB_DEV, LPC_IO_PORT_DECODE_ENABLE, decodes);
 }

+void lpc_disable_decodes(void)
+{
+	uint32_t reg;
+
+	lpc_enable_decode(0);
+	reg = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);
+	reg &= LPC_SYNC_TIMEOUT_COUNT_MASK + LPC_SYNC_TIMEOUT_COUNT_ENABLE;
+	pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg);
+
+	/* D14F3x48 enables ranges configured in additional registers */
+	pci_write_config32(_LPCB_DEV, LPC_MEM_PORT1, 0);
+	pci_write_config32(_LPCB_DEV, LPC_MEM_PORT0, 0);
+	pci_write_config32(_LPCB_DEV, LPC_WIDEIO2_GENERIC_PORT, 0);
+}
+
 uintptr_t lpc_spibase(void)
 {
    u32 base, enables;