22 Mar
2019
22 Mar
'19
8:07 a.m.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31951 )
Change subject: device/pciexp_device: Add set_L1_ss_latency() for pciexp device ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/31951/5/src/device/pciexp_device.c File src/device/pciexp_device.c:
https://review.coreboot.org/#/c/31951/5/src/device/pciexp_device.c@160 PS5, Line 160: if ((cap) && (root->ops->ops_pci != NULL) && suspect code indent for conditional statements (8, 24)
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3d14a40b4ed0dcc216dcac883e33749b7808f00d
Gerrit-Change-Number: 31951
Gerrit-PatchSet: 5
Gerrit-Owner: Subrata Banik subrata.banik@intel.com
Gerrit-Reviewer: Aaron Durbin adurbin@chromium.org
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Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com
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Gerrit-Comment-Date: Fri, 22 Mar 2019 06:07:51 +0000
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