Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55257 )
Change subject: arch/x86/ioapic: Drop irq_on_fsb as a configurable item ......................................................................
arch/x86/ioapic: Drop irq_on_fsb as a configurable item
APIC Serial Bus pins were removed with ICH5 already, so a choice 'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG 0x3 is also not documented since ICH5.
For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was wrong and ignored as BOOT_CONFIG register emulation was never implemented.
For ICH4 and earlier, the choice to use FSB can be made based on the installed CPU model but this is now just hardwired to match P4 CPUs of aopen/dxplplusu.
For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined and the only possible operation mode there is APIC Serial Bus, which requires no configuration.
Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/Kconfig M src/arch/x86/include/arch/ioapic.h M src/arch/x86/ioapic.c M src/drivers/generic/ioapic/chip.h M src/drivers/generic/ioapic/ioapic.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/roda/rk9/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/denverton_ns/lpc.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 18 files changed, 12 insertions(+), 73 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/55257/1
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index a488b55..6a25dae 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -172,14 +172,6 @@ default "src/mainboard/$(MAINBOARDDIR)/cmos.default" depends on HAVE_CMOS_DEFAULT
-config IOAPIC_INTERRUPTS_ON_FSB - bool - default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS - -config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS - bool - default n - config HPET_ADDRESS_OVERRIDE def_bool n
diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index bdbcfbf..9c20cae 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -32,8 +32,7 @@ void setup_ioapic(void *ioapic_base, u8 ioapic_id); void clear_ioapic(void *ioapic_base);
-void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb, - bool enable_virtual_wire); +void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool enable_virtual_wire); #endif
#endif diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index c148534..d57408a 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -109,13 +109,8 @@
}
-void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb, - bool enable_virtual_wire) +void ioapic_set_boot_config(bool irq_on_fsb) { - int first = 0, last; - - set_ioapic_id(ioapic_base, ioapic_id); - if (irq_on_fsb) { /* * For the Pentium 4 and above APICs deliver their interrupts @@ -129,6 +124,13 @@ "IOAPIC: Enabling interrupts on APIC serial bus\n"); io_apic_write(ioapic_base, 0x03, 0); } +} + +void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool enable_virtual_wire) +{ + int first = 0, last; + + set_ioapic_id(ioapic_base, ioapic_id);
if (enable_virtual_wire) { route_i8259_irq0(ioapic_base); @@ -142,6 +144,5 @@
void setup_ioapic(void *ioapic_base, u8 ioapic_id) { - setup_ioapic_helper(ioapic_base, ioapic_id, - CONFIG(IOAPIC_INTERRUPTS_ON_FSB), true); + setup_ioapic_helper(ioapic_base, ioapic_id, true); } diff --git a/src/drivers/generic/ioapic/chip.h b/src/drivers/generic/ioapic/chip.h index 88720bb..9a9395f 100644 --- a/src/drivers/generic/ioapic/chip.h +++ b/src/drivers/generic/ioapic/chip.h @@ -6,7 +6,6 @@ typedef struct drivers_generic_ioapic_config { u32 version; u8 apicid; - u8 irq_on_fsb; u8 enable_virtual_wire; u8 have_isa_interrupts; void *base; diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index 708d9a1..4a8bcf8 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -13,8 +13,7 @@ if (!dev->enabled || !config) return;
- setup_ioapic_helper(config->base, config->apicid, config->irq_on_fsb, - config->enable_virtual_wire); + setup_ioapic_helper(config->base, config->apicid, config->enable_virtual_wire); }
static void ioapic_read_resources(struct device *dev) diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 537841e..c3b6ea6 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -4,7 +4,6 @@ def_bool y select CPU_QEMU_X86 select SOUTHBRIDGE_INTEL_I82801IX - select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE # select HAVE_PIRQ_TABLE diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 5886aff..ae389de 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -143,7 +143,6 @@
chip drivers/generic/ioapic register "have_isa_interrupts" = "1" - register "irq_on_fsb" = "1" register "enable_virtual_wire" = "1" register "base" = "(void *)0xfec00000" device ioapic 2 on end diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 80288bf..4db554b 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -133,7 +133,6 @@
chip drivers/generic/ioapic register "have_isa_interrupts" = "1" - register "irq_on_fsb" = "1" register "enable_virtual_wire" = "1" register "base" = "(void *)0xfec00000" device ioapic 2 on end diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index 3965053..0af9837 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -121,7 +121,6 @@ device pci 1f.0 on # LPC bridge chip drivers/generic/ioapic register "have_isa_interrupts" = "1" - register "irq_on_fsb" = "1" register "enable_virtual_wire" = "1" register "base" = "(void *)0xfec00000" device ioapic 2 on end diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 85d140c..17d506b 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -109,7 +109,6 @@
chip drivers/generic/ioapic register "have_isa_interrupts" = "1" - register "irq_on_fsb" = "1" register "enable_virtual_wire" = "1" register "base" = "(void *)0xfec00000" device ioapic 4 on end diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index e32ae36..fafacc1 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -42,12 +42,6 @@ reg32 |= 0x00270000;
io_apic_write(VIO_APIC_VADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); }
static void enable_hpet(struct device *dev) diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 4950940..1b6936e 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -290,12 +290,6 @@ reg32 |= (redir_entries - 1) << 16;
io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); }
static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = { diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 65be16e..a099c31 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -42,12 +42,6 @@ reg32 |= (PCH_LP_REDIR_ETR - 1) << 16;
io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); }
/* interrupt router lookup for internal devices */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index c6b42ea..caac1b8 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -48,12 +48,6 @@ /* affirm full set of redirection table entries ("write once") */ reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); io_apic_write(VIO_APIC_VADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); }
static void pch_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index f6c04a5..6ff6064 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -50,11 +50,7 @@
set_ioapic_id(VIO_APIC_VADDR, 0x02);
- /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); + ioapic_set_boot_config(VIO_APIC_VADDR, true); }
static void i82801dx_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 9eabf02..ababe67 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -34,12 +34,6 @@ static void i82801gx_enable_ioapic(struct device *dev) { set_ioapic_id(VIO_APIC_VADDR, 0x02); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); }
static void i82801gx_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 6092347..8cc9b42 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -40,12 +40,6 @@ /* affirm full set of redirection table entries ("write once") */ reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); io_apic_write(VIO_APIC_VADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); }
static void pch_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index fb42145..01fff14 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -49,12 +49,6 @@ reg32 |= 0x00270000; } io_apic_write(VIO_APIC_VADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); }
static void pch_enable_serial_irqs(struct device *dev)