[coreboot-gerrit] [XS] Change in coreboot[main]: drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume

[Bill XIE (Code Review)]

Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78288?usp=email )

Change subject: drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume
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Patch Set 5:

(1 comment)

Patchset:

PS4:
> Agree, we shouldn't reset CMOS during S3 resume. […]

GM45 platforms with or without CONFIG(STATIC_OPTION_TABLE) always performs memory training and store the result in CMOS above 128 bytes on every boot, and read it during s3 resume, as shown in raminit_read_training() and raminit_write_training() of nb/intel/gm45/raminit_read_write_training.c.