Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41903
to look at the new patch set (#6).
Change subject: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP WW22 release ......................................................................
vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP WW22 release
This release fixed issues related to FSP_NV_STORAGE HOB. The end of end flow of using memory training data to generate FSP_NV_STORAGE HOB and using memory training data passed from bootloader to skip memory training, works now.
This release attmpted to allow IIO port configuration definition by bootloader, but the issue with PCIe link training persists. On YV3 config A, the onboard NIC card has x4 connection to port 2D. This NIC device is not recognized by FSP.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I70762b377a057d0fca7806f485cce8d479fb5baa --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 3 files changed, 52 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/41903/6