Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30917 )
Change subject: soc/intel/cannonlake: Change in SaGv options ......................................................................
soc/intel/cannonlake: Change in SaGv options
CNL,WHL and CFL all are not using midfixed option in SaGv so keeping it for CNL only and removing it for others.
Change-Id: I754515c2f8e249479c603872c61ac9a006e962ff Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com Reviewed-on: https://review.coreboot.org/c/30917 Reviewed-by: Lijian Zhao lijian.zhao@intel.com Reviewed-by: Subrata Banik subrata.banik@intel.com Reviewed-by: Aamir Bohra aamir.bohra@intel.com Reviewed-by: Maulik V Vaghela maulik.v.vaghela@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/cannonlake/chip.h 1 file changed, 7 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Lijian Zhao: Looks good to me, approved Subrata Banik: Looks good to me, approved Aamir Bohra: Looks good to me, but someone else must approve Maulik V Vaghela: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 947cd65..a877ec1 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -100,12 +100,18 @@ uint16_t FreqSaGvMid;
/* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. + * for CNL options are as following + * When enabled memory will be training at three different frequencies. + * 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled + * for WHL/CFL options are as following * When enabled memory will be training at two different frequencies. - * 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled */ + * 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled*/ enum { SaGv_Disabled, SaGv_FixedLow, +#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE) SaGv_FixedMid, +#endif SaGv_FixedHigh, SaGv_Enabled, } SaGv;