Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34173 )
Change subject: sb/intel/common/spi: Increase flash erase timeout ......................................................................
sb/intel/common/spi: Increase flash erase timeout
This patch provides an increased timeout (60ms -> 1s) for SPI HW-sequencing flash erase operations. Without that the erase for MRC cache writing on siemens/mc_bdx1 sometimes goes wrong because the timeout stops waiting for flash cycle completion. It was found during continuous integration. Investigation showed that the used flash type takes sporadic (e.g. 5% of the test cycles) more time for completion of erasing operation if the ambient temperature increases. The measured time values are in range of data sheet of SPI flash. 60ms is a typical value. So increasing the value is necessary.
tested on siemens/bdx1; measured time values with increased ambient temperature of flash were always smaller than worst case value of 1s.
Change-Id: Id50636f9ed834ffd7810946798b300e58b2c14d2 Signed-off-by: Uwe Poeche uwe.poeche@siemens.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34173 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Werner Zeh werner.zeh@siemens.com --- M src/southbridge/intel/common/spi.c 1 file changed, 1 insertion(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 8430dc8..6fece4f 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -28,7 +28,6 @@ #include <device/device.h> #include <device/pci.h> #include <spi_flash.h> - #include <spi-generic.h>
#include "spi.h" @@ -727,7 +726,7 @@ u32 start, end, erase_size; int ret; uint16_t hsfc; - uint16_t timeout = 1000 * 60; + unsigned int timeout = 1000 * SPI_FLASH_SECTOR_ERASE_TIMEOUT;
erase_size = flash->sector_size; if (offset % erase_size || len % erase_size) {