Christoph Pomaska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35912 )
Change subject: [WIP] Documentation/basics: Add Super I/O section ......................................................................
[WIP] Documentation/basics: Add Super I/O section
This file contains and is supposed to contain basic information about what a Super I/O is and what it does.
Change-Id: If288dcd79c4622a712868229b18f8b38e71d4af9 Signed-off-by: Christoph Pomaska c.pomaska@hosting.de --- A Documentation/basics/superio.md 1 file changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/35912/1
diff --git a/Documentation/basics/superio.md b/Documentation/basics/superio.md new file mode 100644 index 0000000..5f17a4c --- /dev/null +++ b/Documentation/basics/superio.md @@ -0,0 +1,29 @@ +# What is super I/O? + +Super I/O chips are a component that exist in PCs since the 1980s +and are usually connected via ISA/LPC. They are specific to x86 based platforms. + +Super I/O components have a wide range of tasks, from which the most widely known are: +- serial (e.g. RS232) +- PS/2 +- parallel (IEEE 1284) +- floppy-disk-controller +- PECI (Platform Enviroment Controller Interface) + +They can also act as an EC (Embedded Controller) managing things like: +- fancontrol +- battery charge controlling (on laptops) +- LED control + +BMC (Board Management Controller) and manage IPMI (Intelligent Platform Management Interface). +Very most x86 mainboards have at least one Super I/O chip. + +In case of the Supermicro [X10SLM+-F](https://www.supermicro.com/en/products/motherboard/x10slm+-f) there is a Nuvoton NCT6776 and an Aspeed AST2400 used. +The Nuvoton chip manages serial, PS/2 and hardware monitoring while the Aspeed chip manages the BMC functionality. +As another example does the Supermicro X11SSH-TF board solely use the same Aspeed chip as BMC, but also for serial. + + +## Super I/O and coreboot +The registers that need to be configured to make a Super I/O work are mostly vendor-specific, but sometimes also chip-specific. +coreboot ships a tool called [superiotool](../util.md) that reads out the most commonly used registers to determine which chip could be used on the board. +Conveniently it also prints out the registers and their contents in case a superio is detected.