Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30932 )
Change subject: soc/intel/fsp_broadwell_de: Fix TSEG size computation ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/#/c/30932/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/30932/1//COMMIT_MSG@12 PS1, Line 12: Add one MiB to the register value to make TSEG 8MiB instead of 7MiB. : Fixes a crash related to SMRR not matching the TSEG region. this simply looks like a wrong size was programmed for TSEG size.
https://review.coreboot.org/#/c/30932/1/src/soc/intel/fsp_broadwell_de/smmre... File src/soc/intel/fsp_broadwell_de/smmrelocate.c:
https://review.coreboot.org/#/c/30932/1/src/soc/intel/fsp_broadwell_de/smmre... PS1, Line 229: + 1 * MiB; are you sure?
https://review.coreboot.org/#/c/30932/1/src/soc/intel/fsp_broadwell_de/smmre... PS1, Line 241: params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; : params->smrr_base.hi = 0; : params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | : MTRR_PHYS_MASK_VALID; : params->smrr_mask.hi = 0; from my experience it is likely that writing to SMRR hangs the system because base is not aligned to size or that size is not a power of 2.