Hello build bot (Jenkins), Subrata Banik, Pratikkumar V Prajapati, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40363
to look at the new patch set (#4).
Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values ......................................................................
soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values
Add PCIEXBAR register LENGTH offset values to accommodate new SoC implementation.
Changes: 1. The major delta is 0x60:PCIEXBAR register LENGTH offset definition has been changed for latest SoC.
2. Common code takes care of setting the right value for pciex length.
TEST=Able to build CNL, SKL, APL platforms.
Change-Id: I75619be7614f58c96670ef86485d49d4da06ad91 Signed-off-by: Usha P usha.p@intel.com --- M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_def.h M src/soc/intel/common/block/systemagent/systemagent_early.c 3 files changed, 41 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40363/4