Paul Menzel (paulepanter@users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4578
-gerrit
commit f617dbe623e38b68a615a3727542675386ea61e8 Author: Paul Menzel paulepanter@users.sourceforge.net Date: Fri Dec 27 14:14:44 2013 +0100
Revert "amd/car/post_cache_as_ram: Switch stack in assembly rather than in C"
This reverts commit a6c29fe6841ad5e03ddb35803943bed3bc83dfd2 [1].
Testing that change with the Asus M2V-MX SE, resume from suspend to RAM (S3) hangs at `Clearing initial memory region:`.
[…] Mem running ! Ram4 v_esp=000cff28 IN TEST WAKEUP 400CBMEM TOC is at: 7dee0000 CBMEM TOC 0-size: 7e001000 Re-Initializing CBMEM area to 0x7dee0000 Will copy coreboot region to: 7deec000 Copying data from cache to RAM -- switching to use RAM as stack... Done Disabling cache as ram now Clearing initial memory region:
Reverting the commit, resume still fails but goes past the above message until jumping to the image.
[…] Mem running ! Ram4 v_esp=000cff18 testx = 5a5a5a5a IN TEST WAKEUP 400IN TEST WAKEUP 400CBMEM region 7dee0000-7dffffff (cbmem_reinit) Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. CBFS: CBFS_HEADER_ROM_ADDRESS: 0xfffffb90/0x400000 CBFS: CBFS location: 0x0~0x3ffbb0, align: 64 CBFS: Looking for 'fallback/coreboot_ram' starting from 0x0. CBFS: - load entry 0x0 file name (16 bytes)... CBFS: (unmatched file @0x0: cmos_layout.bin) CBFS: - load entry 0x800 file name (32 bytes)... CBFS: (unmatched file @0x800: fallback/romstage) CBFS: - load entry 0xea00 file name (32 bytes)... CBFS: Found file (offset=0xea38, len=61691). CBFS: loading stage fallback/coreboot_ram @ 0x100000 (503872 bytes), entry @ 0x100000 CBFS: stage loaded. Jumping to image.
Therefore revert this change for now until a better tested patch is available.
[1] http://review.coreboot.org/4286
Change-Id: I10f6f1b2c7bbcb501990cd023aafe6e87eab7586 Signed-off-by: Paul Menzel paulepanter@users.sourceforge.net --- src/cpu/amd/car/cache_as_ram.inc | 12 ------------ src/cpu/amd/car/post_cache_as_ram.c | 25 +++++++++++++++---------- 2 files changed, 15 insertions(+), 22 deletions(-)
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 8f0abce..7070cf9 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -414,22 +414,10 @@ CAR_FAM10_ap_out: pushl %ebx /* Init detected. */ pushl %eax /* BIST */ call cache_as_ram_main - /* We will not go back. */
post_code(0xaf) /* Should never see this POST code. */
- .globl cache_as_ram_switch_stack - -cache_as_ram_switch_stack: - /* Return address. */ - popl %eax - /* Resume memory. */ - popl %eax - subl $(( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )), %esp - pushl %eax - call cache_as_ram_new_stack - all_mtrr_msrs: /* fixed MTRR MSRs */ .long MTRRfix64K_00000_MSR diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 3fe496e..eca7673 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -75,11 +75,11 @@ static void vErrata343(void) #endif }
-void cache_as_ram_switch_stack(void *resume_backup_memory); - static void post_cache_as_ram(void) { - void *resume_backup_memory = NULL; +#if CONFIG_HAVE_ACPI_RESUME + void *resume_backup_memory; +#endif #if 1 { /* Check value of esp to verify if we have enough room for stack in Cache as RAM */ @@ -92,6 +92,9 @@ static void post_cache_as_ram(void) } #endif
+ unsigned testx = 0x5a5a5a5a; + print_debug_pcar("testx = ", testx); + /* copy data from cache as ram to ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead. */ @@ -109,19 +112,21 @@ static void post_cache_as_ram(void) vErrata343();
memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline - cache_as_ram_switch_stack(resume_backup_memory); -}
-void -cache_as_ram_new_stack (void *resume_backup_memory); + __asm__ volatile ( + /* set new esp */ /* before CONFIG_RAMBASE */ + "subl %0, %%esp\n\t" + ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) ) + /* discard all registers (eax is used for %0), so gcc redoes everything + after the stack is moved */ + : "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp" + );
-void -cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused))) -{ /* We can put data to stack again */
/* only global variable sysinfo in cache need to be offset */ print_debug("Done\n"); + print_debug_pcar("testx = ", testx);
print_debug("Disabling cache as ram now \n");