Attention is currently required from: Arthur Heymans, Erik van den Bogaert, Felix Held, Frans Hendriks, Paul Menzel, Shelley Chen.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82256?usp=email )
Change subject: soc/intel/braswell/Kconfig: Correct CONFIG_DCACHE_RAM_SIZE ......................................................................
Patch Set 3: Code-Review+1
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82256/comment/6ccd3d28_91dc647f : PS3, Line 10: FSP-T Which FSP are you using? I imagine
https://review.coreboot.org/c/coreboot/+/82256/comment/c6f4173f_3c658f7b : PS3, Line 12: CACHE DCACHE
https://review.coreboot.org/c/coreboot/+/82256/comment/d1a85387_769dda48 : PS3, Line 14: This is a revert of CB:45827 Please reference the commit hash and summary, optionally shortening it:
commit 156bc6f47a7c4536649f79ee037c7eed063d1805 (soc/intel/braswell: Increase dcache size)
Also, I would recommend starting the commit message body with this information, as it's the reason why the value was wrong. Something like this:
soc/intel/braswell/Kconfig: Correct CONFIG_DCACHE_RAM_SIZE
This reverts commit 156bc6f47a7c4536649f79ee037c7eed063d1805 (soc/intel/braswell: Increase dcache size).
Because FSP-T sets up Cache-as-RAM, the value of CONFIG_DCACHE_RAM_SIZE must match the CAR size set up by FSP-T. Otherwise, a ´Wrong CAR region used' warning gets printed in the log.
Because FSP-T returns a size of 0x4000, set CONFIG_DCACHE_RAM_SIZE to 0x4000.
File src/soc/intel/braswell/Kconfig:
https://review.coreboot.org/c/coreboot/+/82256/comment/a6698ca3_ddbe61f1 : PS3, Line 98: The size of the cache-as-ram region required during bootblock : and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE : must add up to a power of 2. Please fix this help text. It should state that the value must match what FSP-T does.