[coreboot-gerrit] Change in coreboot[master]: sb/intel/common/spi: Add Baytrail/Braswell support

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36342 )

Change subject: sb/intel/common/spi: Add Baytrail/Braswell support
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Patch Set 4:

(2 comments)

https://review.coreboot.org/c/coreboot/+/36342/3/src/southbridge/intel/commo... 
File src/southbridge/intel/common/spi.c:

https://review.coreboot.org/c/coreboot/+/36342/3/src/southbridge/intel/commo... 
PS3, Line 281: 	uint32_t sbase;
> Please make use of `uintptr_t`. […]

Done

https://review.coreboot.org/c/coreboot/+/36342/3/src/southbridge/intel/commo... 
PS3, Line 292: 		sbase = pci_read_config32(dev, 0x52);
> Would using defines (like SBASE in SoC) make code mode readable?

Done