Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: haswell: Set up Root Complex topology ......................................................................
haswell: Set up Root Complex topology
System BIOS must program some of the Root Complex Topology Capability Structure registers located in configuration space, specs say. So do it.
Tested on Asrock B85M Pro4, still boots.
Change-Id: Ia2a61706a127bf2b817004a8ec6a723da9826aad Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/southbridge/intel/lynxpoint/lpc.c 3 files changed, 95 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/43744/1
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index baa4f32..e6dfe3a 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -91,6 +91,11 @@ #define GLBIOTLBINV (1 << 1) #define GLBCTXTINV (1 << 0)
+/* Device 0:1.0 PCI configuration space (PCIe Graphics Attach) */ +#define PEG_DCAP2 0xc4 /* 32bit */ +#define PEG_ESD 0x144 /* 32bit */ +#define PEG_LE1D 0x150 /* 32bit */ +#define PEG_LE1A 0x158 /* 64bit */
/* Device 0:2.0 PCI configuration space (Graphics Device) */
@@ -144,6 +149,10 @@ #define EPLE1A 0x058 /* 64bit */ #define EPLE2D 0x060 /* 32bit */ #define EPLE2A 0x068 /* 64bit */ +#define EPLE3D 0x070 /* 32bit */ +#define EPLE3A 0x078 /* 64bit */ +#define EPLE4D 0x080 /* 32bit */ +#define EPLE4A 0x088 /* 64bit */
#define PORTARB 0x100 /* 256bit */
@@ -169,6 +178,8 @@ #define DMIVC1RCTL 0x020 /* 32bit */ #define DMIVC1RSTS 0x026 /* 16bit */
+#define DMIESD 0x044 /* 32bit */ + #define DMILE1D 0x050 /* 32bit */ #define DMILE1A 0x058 /* 64bit */ #define DMILE2D 0x060 /* 32bit */ diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 4311710..25ed828 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -453,12 +453,80 @@ DMIBAR8(0xd34) = 0x44; }
+static void northbridge_topology_init(void) +{ + struct device *dev; + + /* Set the CID1 EP Port Root Topology */ + EPBAR32(EPESD) = (1 << 16); + + EPBAR32(EPLE1D) = (1 << 16) | 1; + EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; + + dev = pcidev_on_root(1, 0); + if (dev && dev->enabled) { + + EPBAR32(EPLE2A) = 0x8000; + EPBAR32(EPLE2D) = (1 << 16) | 1; + + pci_write_config32(dev, PEG_ESD, (1 << 16)); + pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); + pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); + + /* Read and write to lock register */ + pci_or_config32(dev, PEG_DCAP2, 0); + } + + dev = pcidev_on_root(1, 1); + if (dev && dev->enabled) { + + EPBAR32(EPLE3A) = 0x9000; + EPBAR32(EPLE3D) = (1 << 16) | 1; + + pci_write_config32(dev, PEG_ESD, (1 << 16)); + pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); + pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); + + /* Read and write to lock register */ + pci_or_config32(dev, PEG_DCAP2, 0); + } + + dev = pcidev_on_root(1, 2); + if (dev && dev->enabled) { + + EPBAR32(EPLE4A) = 0xa000; + EPBAR32(EPLE4D) = (1 << 16) | 1; + + pci_write_config32(dev, PEG_ESD, (1 << 16)); + pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); + pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); + + /* Read and write to lock register */ + pci_or_config32(dev, PEG_DCAP2, 0); + } + + /* Set the CID1 DMI Port Root Topology */ + DMIBAR32(DMIESD) = (1 << 16) | 1; + + DMIBAR32(DMILE1D) = (2 << 16) | 1; + DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + + DMIBAR32(DMILE2A) = (uintptr_t)DEFAULT_EPBAR; + DMIBAR32(DMILE2D) = (1 << 16) | 1; + + /* Program RO and Write-Once Registers */ + DMIBAR32(DMIPVCCAP1) = DMIBAR32(DMIPVCCAP1); + DMIBAR32(DMILCAP) = DMIBAR32(DMILCAP); +} + static void northbridge_init(struct device *dev) { u8 bios_reset_cpl, pair;
- if (!CONFIG(INTEL_LYNXPOINT_LP)) + if (!CONFIG(INTEL_LYNXPOINT_LP)) { northbridge_dmi_init(); + northbridge_topology_init(); + }
/* Enable Power Aware Interrupt Routing. */ pair = MCHBAR8(INTRDIRCTL); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index f3298b0..85fab4d 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -19,6 +19,7 @@ #include "nvs.h" #include "pch.h" #include <acpi/acpigen.h> +#include <northbridge/intel/haswell/haswell.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/rtc.h> #include <southbridge/intel/common/spi.h> @@ -500,6 +501,18 @@ RCBA32_OR(0x21a8, 0x3); }
+static void pch_topology_init(void) +{ + /* Set component id to 2 for southbridge, northbridge has id 1 */ + RCBA32(ESD) = (2 << 16); + + /* Set target port number and target component id of the northbridge */ + RCBA32(ULD) = (1 << 24) | (1 << 16); + + /* Set target RCRB base address, i.e. DMIBAR */ + RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR; +} + static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: %s\n", __func__); @@ -546,6 +559,8 @@ pch_set_acpi_mode();
pch_fixups(dev); + + pch_topology_init(); }
static void pch_lpc_add_mmio_resources(struct device *dev)