Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34754 )
Change subject: soc/intel/cannonlake: Add provision to skip postcar and load ramstage ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34754/2/src/soc/intel/cannonlake/ro... File src/soc/intel/cannonlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/34754/2/src/soc/intel/cannonlake/ro... PS2, Line 143: set_var_mtrr(mtrr, base, size, MTRR_TYPE_WRPROT);
even overwriting the VAR MTRR that covers CAR region.
This cause sluggishness in romstage code with overridden CAR region
All this, even to add new MTRRs without going through cache-disable-enable sequence, is a grey area. Or I don't have the detailed docs about the non-evict mode to try estimate what will work and what not.
I thought there is good white paper in public domain, i couldn't find that now. never mind i will check how do we make that paper in public. meantime, you can refer to this document, it has some idea about NEM/CQOS mode. https://www.coreboot.org/images/2/23/Apollolake_SoC.pdf